After tapeout: the commercial work of a chip company
First silicon is a major engineering milestone. Packaging, test, software and customer qualification determine how it becomes a saleable product.
Tapeout releases a design for fabrication. It is a costly and consequential milestone, but customers still need a component they can integrate, qualify and obtain in production. Electrical characterisation, packaging and software can expose constraints that the architecture alone could not resolve.
For a semiconductor startup, those dependencies belong in the financing plan from the beginning. The schedule has to accommodate investigation and revision while remaining aligned with the customer's own development programme.
Measure the advantage where the customer uses it
A computing device should be compared on a defined workload, with the numerical precision, memory needs, latency requirements and software environment stated. An accelerator can finish its arithmetic quickly while the application waits for data transfers. A lower power reading at the chip may be partly offset by supporting devices or cooling elsewhere.
Distinguish simulation, engineering samples and production measurements. They answer different questions. A result from a selected sample applies to that sample and its test conditions. Wider claims require characterisation across the operating conditions and variation relevant to the customer's application.
Fabrication is one part of the supply plan
ASML describes fabrication as the repeated construction of patterned layers on a wafer. Lithography, deposition, etching and other processes work together. A fabless company places manufacturing with suppliers, but still has to manage the process choice, design rules, tools, intellectual property interfaces and prototype schedule.
Wafer fabrication
Build the patterned structures and interconnects that form the circuits.
Electrical probing
Test accessible functions on the wafer and identify candidate usable dies.
Package assembly
Connect and protect the die within its mechanical and electrical package.
Final testing
Screen the assembled device against the product's test requirements.
A common sequence for a packaged die; the order and test methods depend on the device and package. Characterisation and customer qualification require additional work.
Packaging and test need named owners and a plan for securing capacity. Their costs and lead times belong beside the wafer plan. First silicon starts another programme of electrical characterisation, fault investigation and system integration. Qualification requirements then depend on where the device will be used.
The package belongs in the architecture
An advanced package can place several dies close together, allowing functions to use different processes or reuse established designs. Those choices introduce electrical, mechanical and thermal dependencies. NIST's advanced packaging programme identifies power delivery, heat removal, testing, repair and reliability among the challenges.
The UCIe specifications define interfaces for communication between dies. They can reduce uncertainty at particular boundaries, but they do not make arbitrary chiplets interchangeable. Specification version, supported protocols, packaging assumptions and implementation compatibility still need to be checked. Test and manageability features also depend on the version and options implemented.
For an assembly with multiple dies, a fault in one die can reduce the value of the completed package. Incoming quality, access for test and fault diagnosis therefore affect the economics of the architecture. These decisions are harder to change once the package design is fixed.
Count saleable devices
Wafer price is one input to unit cost. The model also needs usable dies, assembly costs, test time, rejected units and any supporting hardware shipped to the customer. Separate supplier quotations and measured production results from assumptions. A precise model can still depend heavily on an uncertain yield estimate.
Longer tests may catch defects but add cost and consume equipment capacity. Characterisation explores device behaviour; production screening applies selected tests to manufactured units. The test plan should explain both roles and how design access makes them possible. There is no single yield figure that makes every chip business attractive.
A design win still has dependencies
For programmable devices, compilers, drivers, libraries and debugging tools influence the customer's engineering effort. Test how an unfamiliar engineer installs the tools, runs a representative workload and investigates a fault. Unsupported operations and numerical differences should be visible before a customer commits to migration.
Selection for a customer's design process differs from completed qualification, a production order and recurring shipments. System changes, supply approval and the customer's launch schedule can remain unresolved after a design win. Track those milestones separately when planning revenue and cash requirements.
The development budget should connect each remaining dependency to a test, an owner and enough time to respond to the result. This lets the company identify and finance the work still needed to turn the chip into a product customers can buy.
Sources
- How microchips are made (opens in a new tab)
ASML
- 6 crucial steps in semiconductor manufacturing (opens in a new tab)
ASML
- Assembly & test (opens in a new tab)
Texas Instruments
- National Advanced Packaging Manufacturing Program (opens in a new tab)
NIST
- UCIe Specifications (opens in a new tab)
UCIe Consortium
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